From concept to product production, The De Xilinx FPGA and SoC maps, kits and modules offer you a hardware platform that is immediately ready to use, to speed up your development time and increase your productivity. Partial reconfiguration support for the Kintex 7 and Virtex-7 families is now also available in PlanAhead. Partial reconfiguration dynamically changes logical blocks, while the remaining logic works without interruption. This means that designers can use Virtex 7 or Kintex 7 devices to create flexible systems that can exchange functions and perform remote updates during operation. Partial reconfiguration also allows designers to reduce design costs and size by using time multiplexing, which ultimately results in less diskboard space and minimizes bitstream memory, as smaller or smaller devices can be used. Smaller, smaller appliances can also reduce system power, while replacing power-hungry tasks can reduce the FPGAs` dynamic electricity consumption. If the Artix 7 family support is launched this year with the release of the ISE Design Suite, this will be the first time that Xilinx will offer a partial reconfiguration for the entire range of FPGA families in a single generation. Xilinx is the world leader in programmable platforms. For more information, see www.xilinx.com/. The Vivado® Design Suite offers an IP-centric, IP-centric, next-generation information-focused development environment that has been designed from scratch to address productivity constraints in system-level integration and implementation. « A significant productivity advantage of PlanAhead is the close integration of design, analysis, planning and implementation functions.
For traditional FPGA streams, feedback on critical design settings is late in the design flow, » says Tom Feist, senior director of software and marketing tools at Xilinx. « While the duration of synthesis, location and route remains a priority for Xilinx, reducing the number of design itemes is just as important to accelerate development. Design analysis and preservation flows that ensure that running time is crucial for our customers as we target our new 7-series devices. XilinxBruce Fienberg408-879-4631[email protected]xilinx.com The PlansAhead tool improvements include new activity reports for watchmaking domains, QuickInfo language location and Support for SSO (Simultaneous Switching Output) for BGA BGA packages of 7 Flip-Chip series (FFG) for 7 Flip-Chip-Chip-BGA (FFG) series. With updates to the XPower Estimator (XPE) tool, designers can accurately meet energy consumption forecasts and see how, in most typical designs, Xilinx develops the high-K metal door (HKMG) and a uniform FPGA architecture in all families. To learn more about Xilinx`s lower performance advantage, please visit: www.xilinx.com/power. ISE Design Suite 13 is now available for all ISE editions and lists starting at $2,995 for Logic Edition and now supports Windows 7 32 and 64 bits. Customers can download the trial versions for free at 30 days on the De Xilinx website.